Abstract:
Communication protocols such as UART, and SPI remain widely used across embedded systems, avionics, automotive electronics, and industrial equipment. While these protocols are mature and reliable, their conventional receiver implementations generally report only basic errors (e.g., parity, framing, or synchronization faults). Such mechanisms are insuffcient for detecting subtle or intermittent anomalies caused by transmitterside inconsistencies, hardware degradations, signal integrity variations, or protocol-timing deviations. These irregularities often remain hidden in the testing phase. With advancements in Field-Programmable Gate Arrays (FPGAs), there is increasing potential to embed intelligent diagnostic capabilities directly within communication protocol receivers. This thesis proposes an enhanced approach of implementation and with integrated SelfMonitoring Receiver Implementation (SMRI) framework, a novel FPGA based approach that improves the existing receivers and integrates practical anomaly detection mechanisms into the receiver architecture itself. The SMRI framework is designed to identify issues that may not yet result in incorrect data reception but indicate an increased probability of failure under specifc conditions. The proposed research evaluates this framework using commonly used communication standard UART, and also give a brief touch to its use in SPI Protocol, demonstrating how builtin anomaly detection can enhance system validation, reliability, and predictive fault monitoring during early testing phases
