Cryptography on Risc-V Systems: Ascon Algorithm on Cv32e40x Core Cv-X-If Based ISE using Pynq-Z1 Soc Fpga

Abstract

In 2023 the National Institute of Standards and Technology (NIST) selected Ascon as the standard for lightweight cryptography (LWC), formalized as NIST SP 800-232. As Ascon becomes the basis for confdentiality, integrity and authentication on constrained devices, the cost of accelerating it on RISC-V is a pressing engineering question. RISC-V instruction set extension work has characterized Ascon authenticated encryption and hashing in detail, but three gaps remain: Ascon-MAC, Ascon-PRF and Ascon-PRFShort are largely unaddressed. Every comparable RISC-V work measures the CAESAR-era v1.2 specifcation rather than the standardized algorithms and none reports a single shared hardware permutation core measured on real silicon across the complete seven member family. This thesis therefore establishes what such an accelerator costs in performance, area and power on real hardware, and how its beneft is distributed across the seven members. A CV-X-IF tightly coupled Ascon-p accelerator was designed for a CV32E40X Embedded RISC-V core, synthesized and deployed on a Xilinx Zynq-7000 PYNQ-Z1 FPGA board. It occupies 597 LUTs and 368 flip-flops with no DSP or block RAM, and closes timing at 60 MHz with positive margin. The software baseline and the accelerated run execute on the same bitstream, differing only in one control register bit, and that baseline is hand-written RV32I assembly rather than the compiled C used in the comparable literature, making the ratios conservative. All 28 measurement points, spanning 0 to 1024 bytes and covering AsconAEAD128 under both associated-data conventions, passed NIST Known Answer Test verifcation in both modes. Speedups measured on hardware, not in simulation, range from 2.98x on the single call Ascon-PRFShort to 21.37x on Ascon-Hash256 at 1024 bytes. The area and timing are tool reports, power is a vectorless estimate, and no energy result is claimed. The beneft is not uniform. At a common 16 byte length the seven members span 3.41x to 11.12x from identical hardware, bounded not by the permutation they share but by the non-permutation work accompanying each call. To the author’s knowledge, this is the frst silicon measured characterization of a single shared Ascon accelerator serving the complete seven member SP 800-232 era family on a RISC-V core.