http://hdl.handle.net/123456789/16 Sat, 04 Apr 2026 10:40:42 GMT 2026-04-04T10:40:42Z http://localhost:8080/xmlui/bitstream/id/1039/Published article.png http://hdl.handle.net/123456789/16 http://hdl.handle.net/123456789/7750 A collision avoidance scheme for autonomous vehicles inspired by human social norms Faisal Riaz; Sohail Jabbar; Muhammad Sajid; Mudassar Ahmad; Kashif Naseer; Nouman Ali This paper introduces the novel idea of using human social norms and human emotions to improve the collision avoidance of Autonomous Vehicles (AVs). Until now, the literature has been concerned with theoretical debates regarding ethical issues connected to AVs, while no practical steps have yet been undertaken. This paper introduces the concept of an artificial society of AVs with different personalities and with social norms coded into their autopilot so that they act like well-behaved drivers. For proof of concept, the standard agent modelling tool Netlogo is utilized to simulate the artificial society of AVs. Further- more, comparisons are made with random walk-based non-social-based collision avoid- ance techniques. Extensive testing has been carried out using the behaviour space tool to determine the performance of the proposed approach regarding the number of collisions. A comparative study undertaken with a random walk method indicates that the proposed approach provides a better option for tailoring the autopilots of future AVs, while also promising to be more socially acceptable and trustworthy regarding safe road travel. Mon, 01 Jan 2018 00:00:00 GMT http://hdl.handle.net/123456789/7750 2018-01-01T00:00:00Z http://hdl.handle.net/123456789/7752 Augmenting High-Performance Mobile Cloud Computations for Big Data in AMBER Muhammad Munwar Iqbal; Muhammad Ali; Mai Alfawair; Ahsan Lateef; Abid Ali Minhas; Abdulaziz Al Mazyad; Kashif Naseer Big data is an inspirational area of research that involves best practices used in the industry and academia. Challenging and complex systems are the core requirements for the data collation and analysis of big data. Data analysis approaches and algorithms development are the necessary and essential components of the big data analytics. Big data and high-performance computing emergent nature help to solve complex and challenging problems. High-Performance Mobile Cloud Computing (HPMCC) technology contributes to the execution of the intensive computational application at any location independently on laptops using virtual machines. HPMCC technique enables executing computationally extreme scientific tasks on a cloud comprising laptops. Assisted Model Building with Energy Refinement (AMBER) with the force fields calculations for molecular dynamics is a computationally hungry task that requires high and computational hardware resources for execution.The core objective of the study is to deliver and provide researchers with a mobile cloud of laptops capable of doing the heavy processing. An innovative execution of AMBER with force field empirical formula using Message Passing Interface (MPI) infrastructure on HPMCC is proposed. It is homogeneousmobile cloud platformcomprising a laptop and virtualmachines as processors nodes along with dynamic parallelism. Some processes can be executed to distribute and run the task among the various computational nodes.This task-based and databased parallelismis achieved in proposed solution by using aMessage Passing Interface. Trace-based results and graphs will present the significance of the proposed method. Mon, 01 Jan 2018 00:00:00 GMT http://hdl.handle.net/123456789/7752 2018-01-01T00:00:00Z http://hdl.handle.net/123456789/7754 High-Speed FPGA Implementation of Full-Word Montgomery Multiplier for ECC Applications Safiullah Khana; Khalid Javeedb; Yasir Ali Shaha Modular multiplication is the most crucial operation in many public-key crypto-systems, which can be accomplished by integer multiplication followed by a reduction scheme. The reduction scheme involves a division operation that is costly in terms of computation time and resource consumption both on hardware and software platforms. Montgomery modular multiplication is widely used to eliminate the costly division operation. This work presents an efficient implementation of full-word Montgomery modular multiplication. This incorporates the more efficient Karatsuba algorithm where the complexity of multiplication is reduced form O(n2) to O(n1.58). The Karatsuba algorithm recommends to split the operands into smaller chunks. Two methods of operand splitting are exploited: 1) Four Parts (FP) Splitting and 2) Deep Four Parts (DFP) Splitting. These methods are then used in the design of Integer Multiplier (IM) and Montgomery Multiplier (MM). The design is synthesized using Xilinx ISE 14.1 Design Suite for Virtex-5, Virtex-6 and Virtex-7. Compared with the traditional implementations, the proposed scheme outperforms all other designs in terms of throughput and area-delay product. Moreover, the proposed scheme utilizes the least hardware resources in the known literature. The proposed MM design is able to compute modular multiplication for the Elliptic Curve Cryptography (ECC) field sizes of 192-512 bits. Mon, 01 Jan 2018 00:00:00 GMT http://hdl.handle.net/123456789/7754 2018-01-01T00:00:00Z http://hdl.handle.net/123456789/7755 A high‐speed RSD‐based flexible ECC processor for arbitrary curves over general prime field Yasir Ali Shah; Khalid Javeed; Shoaib Azmat; Xiaojun Wang This workpresents a novel high‐speed redundant‐signed‐digit (RSD)‐based elliptic curve cryptographic (ECC) processor for arbitrary curves over a general prime field. The proposed ECC processor works for any value of the prime number and curve parameters. It is based on a new high speed Montgomery multiplier architecture which uses different parallel computation techniques at both circuit level and architectural level. At the circuit level, RSD and carry save techniques are adopted while pre‐computation logic is incorporated at the architectural level. As a result of these optimization strategies, the proposed Montgomery multiplier offers a significant reduction in computation time over the state‐of‐the‐art. At the system level, to further enhance the overall performance of the proposed ECC processor, Montgomery ladder algorithm with (X,Y)‐only common Z coordinate (co‐Z) arithmetic is adopted. The proposed ECC processor is synthesized and implemented on different Xilinx Virtex (V) FPGA families for field sizes of 256 to 521 bits. On V‐6 platform, it computes a single 256 to 521 bits scalar point multiplication operation in 0.65 to 2.6 ms which is up to 9 times speed‐up over the state‐of‐the‐art. Mon, 01 Jan 2018 00:00:00 GMT http://hdl.handle.net/123456789/7755 2018-01-01T00:00:00Z