http://hdl.handle.net/123456789/10341 2026-10-17T01:49:59Z 2026-10-17T01:49:59Z Ali Raza, 09-242242-001 http://hdl.handle.net/123456789/21856 2026-10-14T08:30:00Z 2026-01-01T00:00:00Z

Cryptography on Risc-V Systems: Ascon Algorithm on Cv32e40x Core Cv-X-If Based ISE using Pynq-Z1 Soc Fpga Ali Raza, 09-242242-001 In 2023 the National Institute of Standards and Technology (NIST) selected Ascon as the standard for lightweight cryptography (LWC), formalized as NIST SP 800-232. As Ascon becomes the basis for confdentiality, integrity and authentication on constrained devices, the cost of accelerating it on RISC-V is a pressing engineering question. RISC-V instruction set extension work has characterized Ascon authenticated encryption and hashing in detail, but three gaps remain: Ascon-MAC, Ascon-PRF and Ascon-PRFShort are largely unaddressed. Every comparable RISC-V work measures the CAESAR-era v1.2 specifcation rather than the standardized algorithms and none reports a single shared hardware permutation core measured on real silicon across the complete seven member family. This thesis therefore establishes what such an accelerator costs in performance, area and power on real hardware, and how its beneft is distributed across the seven members. A CV-X-IF tightly coupled Ascon-p accelerator was designed for a CV32E40X Embedded RISC-V core, synthesized and deployed on a Xilinx Zynq-7000 PYNQ-Z1 FPGA board. It occupies 597 LUTs and 368 flip-flops with no DSP or block RAM, and closes timing at 60 MHz with positive margin. The software baseline and the accelerated run execute on the same bitstream, differing only in one control register bit, and that baseline is hand-written RV32I assembly rather than the compiled C used in the comparable literature, making the ratios conservative. All 28 measurement points, spanning 0 to 1024 bytes and covering AsconAEAD128 under both associated-data conventions, passed NIST Known Answer Test verifcation in both modes. Speedups measured on hardware, not in simulation, range from 2.98x on the single call Ascon-PRFShort to 21.37x on Ascon-Hash256 at 1024 bytes. The area and timing are tool reports, power is a vectorless estimate, and no energy result is claimed. The beneft is not uniform. At a common 16 byte length the seven members span 3.41x to 11.12x from identical hardware, bounded not by the permutation they share but by the non-permutation work accompanying each call. To the author’s knowledge, this is the frst silicon measured characterization of a single shared Ascon accelerator serving the complete seven member SP 800-232 era family on a RISC-V core. Supervised by Dr. Syed Khawar Hussain Shah

2026-01-01T00:00:00Z Naveed Iqbal, 09-242242-007 http://hdl.handle.net/123456789/21857 2026-10-14T08:40:42Z 2026-01-01T00:00:00Z

Enhanced FGPA Implementations of Communication Protocol Receivers with Early Anomaly Detection Capabilities Naveed Iqbal, 09-242242-007 Communication protocols such as UART, and SPI remain widely used across embedded systems, avionics, automotive electronics, and industrial equipment. While these protocols are mature and reliable, their conventional receiver implementations generally report only basic errors (e.g., parity, framing, or synchronization faults). Such mechanisms are insuffcient for detecting subtle or intermittent anomalies caused by transmitterside inconsistencies, hardware degradations, signal integrity variations, or protocol-timing deviations. These irregularities often remain hidden in the testing phase. With advancements in Field-Programmable Gate Arrays (FPGAs), there is increasing potential to embed intelligent diagnostic capabilities directly within communication protocol receivers. This thesis proposes an enhanced approach of implementation and with integrated SelfMonitoring Receiver Implementation (SMRI) framework, a novel FPGA based approach that improves the existing receivers and integrates practical anomaly detection mechanisms into the receiver architecture itself. The SMRI framework is designed to identify issues that may not yet result in incorrect data reception but indicate an increased probability of failure under specifc conditions. The proposed research evaluates this framework using commonly used communication standard UART, and also give a brief touch to its use in SPI Protocol, demonstrating how builtin anomaly detection can enhance system validation, reliability, and predictive fault monitoring during early testing phases Supervised by Dr. Syed Khawar Hussain Shah

2026-01-01T00:00:00Z Amna Waheed Awan, 01-281171-005 http://hdl.handle.net/123456789/18655 2024-11-28T07:40:46Z 2024-01-01T00:00:00Z

Analysis of Physiological Signals for Emotion Charting Amna Waheed Awan, 01-281171-005 Human emotions are complex mental and physiological states that arise in response to various internal and external stimuli. Emotional health is an important part of human physical and psychological health. An emotionally healthy person can perform multiple roles in his life in the best possible way, however, due to emotional imbalance and cognitive disorders a person can face so many physical and mental health issues. Therefore, the timely diagnosis of these mental illness can prevent severe mental disorders and can improve the quality of medical care. Recently, emotion recognition has gained great attention in affective computing and different modalities have been used for emotion recognition i.e. human physical signals and human physiological signals. Human physiological signals are considered to be most reliable source for emotion recognition as compared to human physical signals because they can’t be manipulated. Emotion charting using multimodal signals have grown in popularity due to wide multidisciplinary applications such as health care department, neuromarketing,, robotics, safety, security and e-gaming etc. There are number of physiological markers such as heart rate, respiration, electrodermal activity, conductance and brain activity , which can be used for performing emotion recognition. However, physiological signals such as Electrocardiogram (ECG) signals and Electroencephalograms (EEG) signals measure the cardiac and neuronal activities respectively, connected with different human emotional states . In addition to this, Galvanic Skin Response (GSR) signals are also very highly correlated with the emotional states of human. Therefore, these physiological signals are incorporated in the proposed method and they can be analyzed using different techniques of advanced signal processing and machine learning in order to identify the hidden patterns and classify the emotional states. Previously, researchers have developed different methods for classification of these signals for emotion detection but still there is a need to bridge the connection between the anatomy of human physiological signals and cognitive behaviors by critically analyzing the variation in the waveforms of physiological signals with respect to human emotions. Keeping this in view, this research work proposes two deep learning-based approaches for emotion charting using physiological signals. First approach is an Ensemble method using customized convolutional Stacked Autoencoder (ESA) for Emotion Charting. This approach performs preprocessing of physiological signals (EEG, ECG and GSR) using bandpass filtering and Independent Component Analysis (ICA) followed by Discrete Wavelet Transform (DWT). Then convolutional stacked autoencoder has been employed for feature extraction from the scalograms of physiological signals. Feature vector obtained from stacked autoencoder is then fed to three classifers SVM (Support Vector Machine), RF (Random Forest), and LSTM (Long Short-Term Memory). The outputs of classifers are combined using majority voting scheme for the fnal classifcation of signals into four emotional classes i.e. High Valence and High Arousal (HVHA), Low Valence and Low Arousal (LVLA), High Valence and Low Arousal (HVLA) and Low Valence High Arousal (LVHA). However, second approach is CNN-Vision Transformer (CVT) based emotion charting using ensemble classifcation. In this approach, initially signals are decomposed into non-overlapping segments, the noise is removed using bandpass fltering followed by ICA. Then two feature sets are obtained from 1D CNN and Vision Transformer, which are then combined to generate a single feature vector. Finally feature vector is fed to an ensemble classifer composed of LSTM (Long Short-Term Memory), ELM (Extreme Learning Machine) and SVM (Support Vector Machines) classifiers. The probabilities generated from each classifer is fed as input to few shot learning based technique Model Agnostic Meta Learning (MAML) which combines classifers outputs and generates a single output in the form of emotional classes. The proposed system is validated on AMIGOS and DEAP datasets with 10-fold cross validation and obtained the highest accuracy of 94.75 % , sensitivity of 99.15% and specifcity of 97.61 % with ESA based emotion charting. However, on the other hand the proposed system achieved the highest accuracy of 98.2 %, sensitivity of 98.4% and specifcity of 99.53% with CVT based approach. The proposed system outperforms the state-of-the-art emotion charting methods in terms of accuracy, sensitivity and specifcity. Supervised by Dr. Shehzad Khalid

2024-01-01T00:00:00Z Zahra Waheed Awan, 01-281171-006 http://hdl.handle.net/123456789/18643 2024-11-21T08:32:01Z 2023-01-01T00:00:00Z

Parallel Architecture of Convolutional Neural Network for Object Classification Zahra Waheed Awan, 01-281171-006 Convolutional Neural Networks (CNNs) have been known for their high performance and are widely applied in many computer vision tasks including object detection and image classification. Large-scale CNNs are computationally intensive and require high-computing resources. This issue has been addressed by deploying them on Graphical Processing Units (GPUs). However, GPU-based implementation results in significant power consumption, limiting their application in embedded systems. In this context, FPGA-based implementations offer a reasonable solution with tolerable power consumption, but large-scale CNNs require substantial memory and computation requirements, making it challenging to deploy on resource-limited edge devices. This research work addresses the challenge of deploying CNNs on resource-restricted embedded systems by proposing a memory-efficient parallel architecture (MPA). The goal is to utilize CNN’s inherent parallelism while minimizing memory and power consumption. The MPA approach involves a software/hardware co-design, including a low-memory network compression framework at the software level which removes redundant parameters to reduce model size. In addition, it categorizes layers into No-Pruning (NP) and Pruning (P) layers. Additionally, weight quantization is applied to each category of layers to compress the model further by reducing bits of weight parameters into low-bit width. Depending upon the distribution of the weights, NP-layers undergo Optimized Quantization (OQ), however, P-layers are subjected to Incremental quantization (INQ). We propose OQ algorithm for NP-layers to perform quantization using optimal quantization levels (Q-levels) obtained from the Optimizer. High compression of 11x, 5x, 8.5x and 7.5x has been achieved for LeNet-5, VGG-16. AlexNet and ResNet-50 respectively, by using the proposed compression framework, resulting in significant reduction in memory utilization with negligible accuracy loss. To further minimize the resource utilization of the system, MPA presents a parallel architecture for the convolution (CONV) layers of the model at the hardware level. The compressed model obtained in the previous step is mapped onto target hardware i.e., FPGA by applying the proposed parallel hardware architecture. In parallel architecture, multiple 1D-processing elements (PEs) are connected in parallel as 2D-PE to achieve data-level and computation-level parallelism. Each 2D-PE executes the convolution operation of the CONV layer by performing multiple MAC operations involved in the convolution process in parallel, which further reduces the computational cost of the system. In the structure of each 1D-PE, we further achieve computation-level parallelism by connecting multiple registers, multipliers, adders, and multiplexers in a systolic-array manner. However, for P-layers, multipliers are replaced with barrel shifters to further reduce the system’s resource utilization. The model we have achieved after applying both software and hardware levels optimization is examined based on its resource optimization, which includes the area in terms of number of slice registers, LUTs, DSPs and flipflops. It is found that using barrel-shifter-based PE consumes almost half of the resources as consumed by multiplier-based PE, hence resulting in a prominent decrease in overall resource utilization. Consequently, this makes the proposed system a reasonable solution to be deployed on embedded systems with constrained hardware resources. Supervised by Dr. Shehzad Khalid

2023-01-01T00:00:00Z